The invention relates to a method for fabricating a trench MOS (Metal Oxide Semiconductor) transistor in which at least one trench is formed in a semiconductor body. The trench is then at least partly filled with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer is introduced into the trench in such a way that it has a larger layer thickness in the region of the lower end of the trench than at the upper end of the trench.
Reducing the on resistance is of major importance when developing new generations of DMOS power transistors. Such a reduction of the on resistance makes it possible to reduce the static power loss and at the same time to achieve higher current densities, so that smaller and cheaper chips can be used for the same total current.
For this reason, for a fairly long time now thought has been given to how the on resistance can be reduced in an expedient manner. In principle, this is possible by departing from a planar cell structure and using trench cells. This is because the use of trench cells makes it possible to reduce the channel resistance of a MOS transistor through a significant enlargement of the channel width per unit area. The resistance of the drift path, which is also referred to as the xe2x80x9cepi-resistancexe2x80x9d since the drift path is preferably situated in an epitaxial layer applied on a semiconductor substrate, can be reduced by using deep trenches (in this respect cf. U.S. Pat. No. 4,941,026).
However, deep trenches presuppose that a thicker insulating layer, which in this case is also referred to as a field plate, is used in the lower region of the trenches than in the upper region, i.e. in the channel region, with the actual gate oxide.
In the development of trench MOS power transistors, achieving the required gate oxide quality is a particular challenge. On the one hand, the gate oxide must be grown on a wide variety of crystal orientations, because the trench bottom and the edge or corner lying at the surface of the semiconductor body must also be coated with an insulating layer, that is to say the gate oxide. Since the rate of oxide growth depends on the crystal orientation, this leads to an undesired widening of the thickness distribution of the gate oxide over the trench. The oxidation of the curved silicon areas causes thinnings in the gate oxide and peaks in the silicon of the semiconductor body. This in turn adversely affects the electrical quality of the gate oxide, because the thinnest location determines the breakdown field strength. However, the conductive gate material, in particular doped polysilicon, must be guided out at some location via the edge in order to electrically connect the material. The gate oxide is particularly at risk of having a breakthrough at this location.
A further goal in the development of trench MOS power transistors is to modulate the electric field spikes in the off-state case in such a way that the avalanche multiplication occurs in the semiconductor body and not at an interface. This is because the avalanche breakdown at the interface between semiconductor body and gate oxide would lead to the injection of hot charge carriers into the gate oxide and, consequently, a drifting of the component.
The previous methods for fabricating such trench MOS power transistor cells, in which an insulating layer is thicker in the lower region of the trench than in the upper region, are relatively complicated.
One example thereof is described in U.S. Pat. No. 5,326,711. In this known method, by way of example, polycrystalline silicon has to be deposited three times in total in the fabrication process in order to configure the trench in the desired manner.
In a method disclosed in Published European Patent Application No. EP 0 666 590 A2 or in U.S. Pat. No. 5,783,491, the quality of the gate dielectric is improved through the use of two-fold oxidation (xe2x80x9csacrificial oxidexe2x80x9d) and etching-away of the oxide. This achieves a certain rounding of the silicon edges.
It is accordingly an object of the invention to provide a method for fabricating a trench MOS power transistor which overcomes the above-mentioned disadvantages of the heretoforeknown methods of this general type and with which it is possible to fabricate a trench with a thicker insulating layer in a lower region than in an upper region in a simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a trench MOS power transistor, the method includes the steps of:
forming a trench in a semiconductor body;
coating walls and a bottom of the trench with a first insulating film of a given final thickness by applying the first insulating film as a plurality of thermally oxidized and deposited layers;
filling a lower end of the trench with an auxiliary layer;
removing the first insulating film in regions not coated with the auxiliary layer;
removing the auxiliary layer;
growing a second insulating film on uncovered walls at an upper end of the trench such that the second insulating film is thinner than the given final thickness of the first insulating film;
filling the trench at least partly with a conductive material such that the conductive material is insulated from an inner surface of the trench by the first insulating layer and the second insulating layer; and
introducing source zones and body zones into the semiconductor body and providing metallization layers for providing contacting connections.
In other words, in the case of the method for fabricating a trench MOS power transistor, in which at least one trench is introduced into a semiconductor body, which trench is then at least partly filled with a conductive material which is isolated from the inner area of the trench by an insulating layer, the insulating layer being introduced into the trench in such a way that it is provided with a larger layer thickness in the region of the lower end of the trench than at the upper end thereof, the object of the invention is achieved by virtue of the fact that:
(a) the at least one trench is introduced into the semiconductor body,
(b) the walls and the bottom of the trench are coated with a first insulating film, which is formed as a multi-layer system of thermally oxidized and deposited layers;
(c) the lower end of the trench is filled with a first auxiliary layer,
(d) those parts of the first insulating film which are not coated with the first auxiliary layer are removed,
(e) the auxiliary layer is removed,
(f) a second insulating film, which is thinner than the final thickness of the first insulating film, is grown on the uncovered walls of the trench,
(g) the trench is filled with the conductive material, and
(h) source and body zones are introduced into the semiconductor body, and metallization layers are provided for contact connection of these zones.
If the intention is to prevent the removal of the first insulating film in specific regions, which may be the case at the edge, then a further auxiliary layer is applied as masking in these regions. It is also possible to depart from the order specified, for example by making the source and body zones first.
With the method according to the invention, a structure is proposed which both alleviates the critical locations with regard to gate oxide quality and, in the active region, permits modulation of the field distribution through the use of a trench field plate. The actual MOS structure of the transistor with the gate oxide is situated in the upper part of a trench. In the lower part of the trench, the dielectric (field plate) is thicker than the gate oxide. As a result, a higher voltage can be dropped across the dielectric, which permits deeper trenches and a lower on resistance Ron. The transition between gate oxide and field plate oxide is preferably graduated. An abrupt transition would lead to unfavorable field spikes in the silicon. The trenches can be provided both in cells and strips and in any other geometric forms.
In step (c) above, the trench can also be filled with the first auxiliary layer and etched back, so that the first auxiliary layer remains at the lower end of the trench.
The gate material is routed to the surface of the semi-conductor body via thick oxide, which means that the electric field strength in the oxide is alleviated at critical edges.
For the semiconductor body, a silicon substrate which is highly doped with boron may preferably be used as starting material, onto which a p-conducting epitaxial layer with a dopant concentration of 1xc3x971014 to 1xc3x971018 charge carriers cmxe2x88x923 is deposited. The etching of the trench can then be performed in a customary manner with the aid of a patterned trench mask, which is composed of silicon dioxide, for example. After the fabrication of the trenches, this trench mask is removed.
The trenches themselves may be embodied as strips or else as lattices for a cell structure. In this case, the width of the trenches should be greater than twice the width of a first insulating film that is applied later and is made, for example, of silicon dioxide (field oxide).
This first insulating film is applied with a layer thickness which depends on the voltage class for which the trench MOS transistor cell is intended to be used. In this case, the layer thickness may range from below 0.1 xcexcm to a few xcexcm. If the intention is to avoid steps of the insulating film at the later upper edge thereof, then it is expedient to use a multilayer system for the first insulating film, that is to say to configure the first insulating film from a plurality of layers including, for example, thermal silicon dioxide through thermal oxidation of the trench-etched semiconductor body and a deposited silicon dioxide (TEOS). As an alternative, these materials can also be used for the first insulating film if the latter includes only one layer.
By way of example, a photoresist may advantageously be used for the first auxiliary layer, which photoresist firstly extends to above the silicon edge of the semi-conductor body and is then etched back in the trenches to below the so-called xe2x80x9cbody lower edgexe2x80x9d, an n-conducting well in the p-conducting epitaxial layer. When photoresist is used for the auxiliary layer, a thermal treatment (xe2x80x9cpostbakexe2x80x9d) is preferably performed.
If inactive trenches are intended to be produced then the corresponding regions of the first insulating film may be masked with a further auxiliary layer. Photoresist, for example, may be used for this further auxiliary layer.
After the application of the auxiliary layer, the first insulating film is etched isotropically in a wet-chemical manner, for example, so that the first insulating film remains only below the first auxiliary layer. Afterward, the first auxiliary layer is removed. The gate insulating layer made, for example, of silicon dioxide, the so-called gate oxide, is then grown, whose layer thickness is between a few nm to in excess of 100 nm depending on the intended threshold voltage of the trench MOS transistor cells. What is important, however, is that this gate insulating layer which forms the second insulating film is thinner than the end thickness of the insulating film.
Apart from one exception, the further fabrication of the trench MOS transistor cell is effected in a customary manner:
The body region, masked by the first insulating film or by a dedicated phototechnology, is made by using an implantation and an out-diffusion. The gate material, in particular poly-crystalline silicon, is then deposited and doped. After a patterned etching-back of the gate material to below the silicon upper edge of the semiconductor body, the gate material may, if appropriate, subsequently be sealed with an insulating layer made of silicon dioxide, in order to prevent outdiffusion of dopants. This order of diffusion of the body region and patterning and/or sealing of the gate material could, if appropriate, also be changed, i.e. reversed.
It is now advantageous if a so-called xe2x80x9cbody reinforcementxe2x80x9d, is introduced. This is preferably done by implantation of an n+-conducting zone in the n-conducting body region, if the semiconductor substrate is p-conducting. It goes without saying that the respective conduction types can also be reversed. This body reinforcement brings about a reduction of the breakdown voltage of the MOS transistor cell at the step between the first thicker insulating film and the second thinner insulating film, i.e. at the so-called oxide step in the trench. A preferred dopant concentration for the body reinforcement is about 1xc3x971018 charge carriers cmxe2x88x923.
The body reinforcement, which is preferably implanted, and further dopings may also be introduced at a different point in time, for example at the start of the process.
There then follows an implantation of the source zone, in which case this implantation can be masked by the first insulating film or a dedicated phototechnology. After the deposition of a dielectric made, for example, of silicon dioxide for the insulation of gate a source metallization layer, the contact holes are etched.
A masked implantation of an n++-conducting body contact, which, if appropriate, is performed for each trench MOS transistor cell, is followed by the customary metal deposition using, for example, aluminum for the source zone and the body contact. The metallization layer applied through the use of the metal deposition is then patterned, whereupon a passivation may also follow.
Another mode of the method according to the invention includes, subsequent to coating the walls and the bottom of the trench with the first insulating film, applying a silicon nitride layer on the first insulating film and patterning the silicon nitride layer.
Yet another mode of the method according to the invention includes providing the silicon nitride layer with a layer thickness of substantially 20 nm.
Another mode of the method according to the invention includes the step of patterning the auxiliary layer and the first insulating film by using a single photoresist layer and a mask and by exposing the single photoresist layer only down to a given depth.
A further mode of the method according to the invention includes the step of covering inactive trenches by introducing a first photoresist layer into the inactive trenches and patterning the first insulating film by using a second photoresist layer applied outside the first photoresist layer.
Another mode of the method according to the invention includes the step of applying the second photoresist layer subsequent to applying the first photoresist layer.
To summarize, the invention has in particular the following advantages:
good gate oxide quality through alleviation of edges and corners; nowhere in the transistor is gate material routed via gate oxide at critical edges;
thick oxide of the first insulating film in the bottom of the trench in order to withstand high drain-gate voltages;
stepped transition between first and second insulating films along a trench for high voltages at the edge; and
field plate effect through the deep trench for reducing the Ron component of the body or drift zone.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a trench MOS power transistor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.